VSDSquadron

Packages

VSDSquadron board (fully functional)

The VSDSquadron board comes with a minimum of 10 GPIOs, which makes it ideal for a diverse range of projects. The board specifications are provided here, and a USB cable is included for easy programming, allowing you to start your projects promptly. Additionally, a list of applications that can experiment with on the board are listed below.(Parts used for demo applications are not included in the Kit) 

1. Line Follower
2. 4-digit seven segment
3. Servo motor
4. IOT and home automation
5. And many more

VSDSquadron board (BYOC – Bring your own Chip)

This offer is only for participants of the Sky130 Google Shuttle or ChipIgnite programs who want to use the VSDSquadron board for their own chips. You will receive just the PCB without the Caravel chip mounted on, and you will have to solder your own Caravel chips on the PCB to make it functional.

VSDSquadron kit (complete education kit)

The complete education kit contains 1 or more VSDSquadron boards and full access to about 60 modules/videos and labs.

Our labs are designed to help you get started with RISC-V programming, synthesis, physical design, and circuit design. We’ve included pre-compiled packages for all the tools you’ll need, including software, PDKs, and more. We recommend using Ubuntu 20.04 or above for best results.

Modules Name	Chapters
VLSI Ed-Tech Introduction	The Big Picture-Need for RISC-V
Introduction to RISC-V ISA and GNU compiler toolchain	Introduction to RISC-V basic keywords
	Labwork for RISC-V software toolchain
	Integer number representation
Introduction to ABI and basic verification flow	Application Binary interface (ABI)
	Lab work using ABI function calls
	Basic verification flow using iverilog
Need for IP design	The Big Picture – IP design Specs to GDS flow
IP design Prerequisite – Basics of NMOS Drain current (Id) vs Drain-to-source Voltage (Vds)	Introduction to Circuit Design and SPICE simulations
	NMOS resistive region and saturation region of operation
	Introduction to SPICE
IP design Prerequisite – Velocity saturation and basics of CMOS inverter VTC	SPICE simulation for lower nodes and velocity saturation effect
	CMOS voltage transfer characteristics (VTC)
IP design Prerequisite – CMOS Switching threshold and dynamic simulations	Voltage transfer characteristics – SPICE simulations
	Static behavior evaluation – CMOS inverter robustness – Switching Threshold
IP design Prerequisite – CMOS Noise Margin robustness evaluation	Static behavior evaluation – CMOS inverter robustness – Noise margin
IP design Prerequisite – CMOS power supply and device variation robustness evaluation	Static behavior evaluation – CMOS inverter robustness – Power supply variation
	Static behavior evaluation – CMOS inverter robustness – Device variation
Analog IP design example	IP design example using ALIGN Opensource Tool for Analog Circuit Layout Synthesis
Introduction to Macros	The Big Picture – What are Macros?
Introduction to Verilog RTL design and Synthesis	Introduction to open-source simulator iverilog
	Labs using iverilog and gtkwave
	Labs using Yosys and Sky130 PDKs
	Labs using Yosys and Sky130 PDKs
Timing libs, hierarchical vs flat synthesis and efficient flop coding styles	Introduction to timing .libs
	Hierarchical vs Flat Synthesis
	Various Flop Coding Styles and optimization
Combinational and sequential optimizations	Introduction to optimizations
	Combinational logic optimizations
	Sequential logic optimizations
	Sequential optimizations for unused outputs
GLS, blocking vs non-blocking and Synthesis-Simulation mismatch	GLS, Synthesis-Simulation mismatch and Blocking/Non-blocking statements
	Labs on GLS and Synthesis-Simulation Mismatch
	Labs on synth-sim mismatch for blocking statement
Inception of open-source EDA, OpenLANE and Sky130 PDK	How to talk to computers
	SoC design and OpenLANE
	Get familiar to open-source EDA tools
Good floorplan vs bad floorplan and introduction to library cells	Chip Floor planning considerations
	Library Binding and Placement
	Cell design and characterization flows
	General timing characterization parameters
Design library cell using Magic Layout and ngspice characterization	Labs for CMOS inverter ngspice simulations
	Inception of Layout – CMOS fabrication process
	Sky130 Tech File Labs
Pre-layout timing analysis and importance of good clock tree	Timing modelling using delay tables
	Timing analysis with ideal clocks using openSTA
	Clock tree synthesis TritonCTS and signal integrity
	Timing analysis with real clocks using openSTA
Final steps for RTL2GDS using TritonRoute and openSTA	Routing and design rule check (DRC)
	Power Distribution Network and routing
	TritonRoute Features
Mixed Signal SoC Design and Full Chip RTL2GDS	The Big Picture – SoC Design
	Mixed-signal full chip SoC design and implementation
Project Work – Chip Testing planning	The Big Picture – VSDSquadron board planning and verification
	Caravel Chip Details
	RISC-V summary
	VSDSquadron firmware
	VSDSquadron FT232 and Flash Operation
	VSDSquadron Reset Flow and Boot Process
Project Work -Using “VSDSquadron” development of  RISC-V application	Coming up You will get access to projects that our students are currently conducting with the VSDSquadron, like the Linefollower

Crowdfunding Plan

The funding campaign runs from 30.May 2023 to 30. June 2023. The money collection phase will be in July. Production for up to 1000 boards is planned for August 2023, Shipment for the first 1000 boards is planned for August 2023. For orders beyond 1000 boards we will have to order additional production runs for the parts, which can delay the delivery by several months.

Shipping Policies

• If you believe that the product is not in good condition, or if the packaging is tampered with or damaged, before accepting delivery of the goods, please refuse to take delivery of the package, and Contact us (+91-8548037643), mentioning your order reference number. We shall make our best efforts to ensure that a replacement delivery is made to you as soon as possible.
• Please note all items will be shipped with an invoice mentioning the price, as per Indian Tax Regulations.

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Canceling An Order:

• Order cancellation may attract 5% bank charges depending on the payment methods used by customer.(It is because most payment gateway providers collect their Commission even though an order was cancelled and refunded.).
• Due to the nature of the products we are selling and our strict quality policy, we are unable to offer order cancellation and return without valid reason.

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100% Refund/Replacement:

• We guarantee to provide accurate descriptions and high quality products as mentioned in the website. In order to protect customers from shipping damage, item mismatch or parts missing etc., we are providing 24 hours time (From the date of order delivery) to report the complaint by email at contactvsd@vlsisystemdesign.com
• Our technical team will verify the submitted details visually and will issue a new Kit. Once we received the Kit our experts will verify the issue reported and will send the replacement items to the customer shipping cost prepaid by us. In case, we do not have the kit in stock to provide replacement, we will issue 100% refund.
• Furthermore, no warranty will apply if the Product has been subject to misuse, static discharge, neglect, accident, modification, or has been soldered or altered in any way.
• Due to the nature of the products we are selling and our strict quality policy, we are unable to offer order cancellation and return without valid reason.

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Limits Of Responsibility:

We accept no responsibility for improper installation of our products. Electrical polarity must be properly observed in hooking up electrical components.

Risks:

We have received the prototypes from the factory and have tested the prototypes successfully. Delays for the electronic parts that we need to source are unlikely but not impossible. If we would detect problems with the chips or the boards, we will inform you about the delay (likely several months) and you will be able to cancel your backing if you don’t want to wait for a flawless product.

Updates:

11.1.2023: Initial draft of the campaign

15.4.2023: Second draft of the campaign

24.5.2023: Third draft of the campaign

30.5.2023: Launch of the campaign

Campaign status